1. Field of the Invention
The present invention relates to a system decoder and method for an optical disc playback device, and more particularly to a system decoder and method for a digital video (or versatile) disc playback device.
2. Description of the Related Art
The digital video disc, which is one type of digital animation disc medium, is a popularized next generation multimedia storage device for storing high grade images with a high degree of tone quality.
Referring to FIG. 1, when playing back a disc 100, a disc motor 160 starts to rotate at a speed, and the optical pickup, having a head 120, converts the disc information into a high frequency analog signal (HF) to be transmitted. This HF signal is shaped into a pulse waveform, whereby an eight-to-sixteen modulation (ESM) or eight-to-fourteen modulation (EFM) data stream is delivered to a phase locked loop (hereinafter referred to as "PLL") 300 and to a system decoder 200. The system decoder 200 performs demodulation, error correction and descrambling of the (ESM, EFM) data stream. A microcomputer 500 is a device control unit for controlling the overall operation of the entire optical disc playback system. When receiving a data transfer start signal from an audio/video decoder 600 or ROM decoder, which is described below, the microcomputer 500 generates a transfer control signal.
The above mentioned PLL 300 consists of a phase comparator, a voltage-controlled oscillator and a frequency divider, and it generates a first clock synchronized with a signal reproduced from the specific optical disc. A disc drive controller 400 controls the constant linear velocity of the disc and other disc-related operations by considering frequency and the phase servo signals according to a frame synchronizing signal Sf provided from a synchronous detector 220. The audio/video decoder 600 performs operations for sorting data output from the system decoder 200 into audio and video data to reproduce the original audio and video data recorded on the disc. The audio and video data demodulated by the audio/video decoder 600 are delivered to an NTSC (or PAL) encoder 700 and to a digital analog converter 800, respectively, thereby being output to a monitor 960 and a speaker 970, respectively. A ROM decoder 950 is typically built into a host (for example, a personal computer) and operated by instructions thereof, which transfers data from the system decoder 200 to the host (computer) according to a specific interface method.
Referring to FIGS. 1 and 2, first and second memories 330, 280 are employed, which are static and dynamic RAMs, respectively, in which the former is used for error correction and the latter is used for data buffering. That is, data retrieved from the disc 100 is demodulated to its state prior to recording and is stored in the first memory 330. The data stored in the first memory 330 is retrieved in units of blocks and delivered to and corrected by an error corrector 230. The data, corrected by error corrector 230, is then stored again in the first memory 330. The descrambler performs descrambling with respect to the error corrected data retrieved from the first memory 330 and stores descrambled data in the second memory 280.
The data stored in the second memory 280 is retrieved to be transferred to the audio/video decoder 600 or to the ROM decoder 950. The audio/video decoder 600 sorts the data transmitted from the system decoder 200 into audio and video data, respectively, in order to reproduce the original audio and video data, respectively. The built-in ROM decoder 950 within the host (for example, a personal computer) is operated by instructions of the host, thereby transferring the data from the system decoder 200 to the host (computer) according to the specific interface method.
The first and second memory controllers 320, 270 perform functions to generate addresses and to prevent over-flow and under-flow conditions, etc. for the first and second memories 280, 330, respectively. As mentioned above, since the conventional system decoder 200 includes separate memories for error correcting and data buffering, and accordingly, includes separate respective memory controllers, the construction of the system decoder becomes not only complicated and expensive, and also makes it difficult to miniaturize products incorporating the same.